Self-Immunity Technique to Improve Register File Integrity

Faarok Syed, Dr.V.Venkata Rao

Abstract


Continuous shrinking in feature size, increasing power density etc. increase the vulnerability of microprocessors against soft errors even in terrestrial applications. The register file is one of the essential architectural components where soft errors can be very mischievous, because errors may rapidly spread from there throughout the whole system. Thus, register files are recognized as one of the major concerns when it comes to  reliability. This paper introduces Self-Immunity, a technique  that improves the integrity of the register file with respect to soft errors. Based on the observation that a certain number of register bits are not always used to represent a value stored in a register. This paper deals with the difficulty to exploit this obvious observation to enhance the register file integrity against soft errors. We show that our technique can reduce the  vulnerability of the register file considerably while exhibiting  smaller overhead in terms of area and power consumption compared to state-of-the-art in register file protection.

Keywords


Registers, Self-Immunity, Soft Errors, Vulnerability

References


Greg Bronevetsky and Bronis R. de Supinski, ”Soft Error Vulnerability of Iterative Linear Algebra Methods,” in the 22nd annual international conference on Supercomputing, pp. 155-164,2008.

J.L. Autran, P. Roche, S. Sauze, G. Gasiot, D. Munteanu, P. Loaiza,M. Zampaolo and J. Borel, “Real-time neutron and alpha soft-errorrate testing of CMOS 130nm SRAM: Altitude versus underground measurements,” in ICICDT‘08, pp. 233–236, 2008.

S.S. Mukherjee, C. Weaver, J. Emer, S.K. Reinhardt and T. Austin,“A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor,” in International Symposium on Microarchitecture (MICRO-36), pp. 29-40, 2003.

T.J. Dell, “A whitepaper on the benefits of Chippkill-Correct ECC for PC server main memory,” in IBM Microelectonics division Nov 1997.

S. Kim and A.K. Somani, “An adaptive write error detection technique in on-chip caches of multi-level cache systems,” in Journal of microprocessors and microsystems, pp. 561-570, March 1999.

G. Memik, M.T. Kandemir and O. Ozturk, “Increasing register fileimmunity to transient errors,” in Design, Automation and Test in Europe, pp. 586-591, 2005.

Jongeun Lee and Aviral Shrivastava, “A Compiler Optimization toReduce Soft Errors in Register Files,” in LCTES 2009.

Jason A. Blome, Shantanu Gupta, Shuguang Feng, and Scott Mahlke, “Cost-efficient soft error protection for embedded microprocessors,” in CASES ’06, pp. 421–431, 2006.

P. Montesinos, W. Liu, and J. Torrellas, “Using register lifetime predictions to protect register files against soft errors,” in Dependable Systems and Networks, pp. 286–296, 2007.

M. Rebaudengo,M. S. Reorda, and M.Violante, “An Accurate Analysis of the Effects of Soft Errors in the Instruction and Data Caches of a Pipelined Microprocessor,” in DATE’03, pp. 602-607, 2003.

I. Koren and C. M. Krishna, Fault-Tolerant Systems. San Mateo, CA: Morgan Kaufmann, 2007.

MiBench (http://www.eecs.umich.edu/mibench/).

T. Slegel et al, “IBM’s S/390 G5 microprocessor design,” in IEEE Micro, 19, pp. 12-23, 1999.

M. Fazeli, A. Namazi, and S.G. Miremadi “An energy efficient circuit level technique to protect register file from MBUs and SETs in embedded processors,” in Dependable Systems & Networks 2009, pp. 195–204, DNS’09.

K. Walther, C. Galke and H.T. VIERHAUS, “On-Line Techniques for Error Detection and Correction in Processor Registers with Cross-Parity Check,” in Journal of Electronic Testing: Theory and Applications 19, pp.501-510, 2003.

M. Spica and T.M. Mak, “Do we need anything more than single bit error correction (ECC)”, in Memory Technology, Design and Testing, Records of the International Workshop on 9-10, pp. 111–116, 2004.

M. Kandala, W. Zhang, and L. Yang, “An area-efficient approach to improving register file reliability against transient errors,” in Advanced Information Networking and Applications Workshops, AINAW '07, pp. 798–803, 2007.

http://archc.sourceforge.net/.

Jun Yan and Wei Zhang, “Compiler-guided register reliability improvement against soft errors,” in EMSOFT ’05, pp. 203–209, 2005.

E. Touloupis, J.A. Flint, V.A. Chouliaras and D.D. Ward, “Efficient protection of the pipeline core for safety-critical processor-based systems,” in IEEE workshop on Signal Processing Systems Design and Implementation, pp. 188-192, 2005.

Jongeun Lee and A. Shrivastava, “A Compiler-Microarchitecture Hybrid Approach to Soft Error Reduction for Register Files,” in Computer-Aided Design of Integrated Circuits and Systems, pp. 1018-1027, 2010.

Jongeun Lee and A. Shrivastava, “Compiler-managed register file protection for energy-efficient soft error reduction,” in ASP-DAC, pp.618–623, 2009.

Riaz Naseer, Rashed Zafar Bhatti, and Jeff Draper, “Analysis of Soft Error Mitigation Techniques for Register Files in IBM Cu-08 90nm

Technology,” in MWSCAS’06, pp. 515-519, 2006.


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